1. Field of the Invention
The present invention relates generally to a method for deriving signal constraints to accelerate sequential test generation, and more particularly pertains to a method for accelerating sequential test generation algorithms for large sequential circuits by using signal constraints which provide information about sets of logic values that signals in the sequential circuit can or cannot assume for any input sequence. The method iteratively uses symbolic simulation in conjunction with 3-valued signal probabilities and line justification to refine the set of values that a signal can assume to efficiently compute the signal constraints.
2. Discussion of the Prior Art
Test generation for sequential circuits is significantly more difficult than combinational circuits due to the presence of memory elements. Hardware modifications like full scan design or partial scan design are being employed widely to alleviate the test generation problem. Design modifications render all or a subset of flip-flops to be completely controllable and observable. This implies that arbitrary logic values can be loaded into the scan flip-flops and circuit responses collected in any of the scan flip-flops can be observed. These modifications entail modest area and performance penalties but they can significantly increase the test application time and the size of the test set. Non-scan or partial scan designs may be more desirable because they incur fewer penalties than full-scan designs. However, these designs require a sequential test generator for deriving test sequences. The present invention speeds up sequential test generators without adversely affecting the fault coverages achievable using these tools.